1) Field of the Invention
The present invention relates to a programmable logic device suitable for use as a logic device such as an FPGA (Field Programmable Gate Array), a CPLD (Complex programmable Logic Device) in which the function thereof can be changed in accordance with a program. The present invention also relates to a method of controlling a clock signal supplied to the programmable logic device.
2) Description of the Related Art
A programmable logic device represented by a device such as an FPGA or CPLD is a logic device of which operation can be changed in accordance with a program. The programmable logic device has an advantageous nature that makes it possible to handle various kind of problems such as specification change of the product which will be brought about at an early stage of product development. For this reason, recently, technology of the logic device is rapidly developed.
Since the logic device tends to suffer from restriction when a desired circuit scale is realized or when operation speed thereof is to be increase, the programmable logic device is frequently utilized as a trial manufacture of an LSI (Large Scale Integration) at a stage of experiment and development. However owing to the recent development of device technology, allowable circuit scale is enlarged and the operation speed is increased, with the result that the logic device becomes more and more utilized practically. In particular, the logic device is frequently utilized in a part of system serving as an interface with an external system where it is difficult to construct the part of system with a microprocessor unit or a digital signal processor.
However, when the logic device is applied to a system such as a mobile communication terminal or a portable telephone, a rate of power consumption is a decisive factor, in addition to the operation speed and the circuit scale, upon selecting a device. When a programmable logic device is designed in a conventional manner, since the circuit size or the operation speed is regarded as a priority factor, the rate of power consumption has not reached a satisfactory level as compared with an LSI designed for a specific use.
In general, when the device of the rate of power consumption is large, the generated heat amount also is increased. This heat amount will influence upon the circuit operation of the device. For example, if a system employing the device is one provided outdoors which can be supplied with electric power from a power supply, the problem of power consumption reduction will not be a serious problem for such a system as compared with the above-described system such as a mobile communication terminal. However, if the device is employed in the system such as a mobile communication terminal, to suppress the heat generation due to the electric power consumption becomes a more important factor.
That is, if a circuit device having a high heat generating nature is employed in a system, a cooling device is requested for guaranteeing the operation of the circuit, which leads to a cost increase in the system. Thus, when a programmable logic device is applied to the above-described system, in order to guarantee a proper circuit operation, it is requested to employ a circuit device having a properly suppressed heat generating nature in the system upon designing the system.
FIG. 8 is a circuit diagram showing a part of an FPGA as an example of a conventional programmable logic device. As shown in FIG. 8, an FPGA 100 is arranged to include a plurality (there are shown 16 blocks in FIG. 8) of logic blocks (CLB:Configuration Logic Block) 101 arrayed in a matrix fashion,lines 102 extended to form a grid, line-changing switches 103 provided at respective intersecting points of the lines 102 extended to form a grid, and a clock net 104 for delivering a clock signal to the logic blocks 101.
The wiring 102 connect each of the logic blocks 101 one another. The line-changing switch 103 is a unit for changing the connection relation through the lines 102 by programming. The connection relation among the logic blocks 101 can be changed by the switching of the line-changing switch 103. Thus, a function implemented by the circuit can be changed in accordance with the program. The clock net 104 is provided independently of the lines 102 which connect the logic blocks 101 one another. In other words, the clock net 104 is ordinarily not connected to the lines 102.
Meanwhile, the logic block 101 is made up with integrated circuit elements such as flip-flops constituting a sequential circuit and AND gates, OR gates and so on for realizing logic operation. In particular, if the flip-flop function within the logic block 101 is constructed by a CMOS (Complementary Metal Oxide Semiconductor), electric power consumed by the flip-flop circuit portion will be increased. Therefore, if the electric power consumed at the flip-flop circuit portion can be successfully suppressed, then electric power consumption in the whole FPGA can be remarkably reduced.
If an enable terminal is provided at the flip-flop circuit portion within the above-described logic block 101, a signal can be supplied to the enable terminal so that the flip-flop operation can be controlled in switching between the enable mode and the disable mode in synchronism with the clock signal. However, the clock signal itself is inevitably delivered to the flip-flop circuit portion even if the flip-flop circuit portion is brought into the disable mode. Therefore, the electric power will be uselessly consumed at the flip-flop circuit portion due to the clock signal which is inevitably supplied to the flip-flop circuit portion during the disable mode.
For this reason, if electric power consumption is suppressed in the programmable logic device such as the FPGA described with reference to FIG. 8, it is desirable for the signal to be prevented from being delivered in the logic block 101 at the flip-flop circuit portion thereof when the flip-flop circuit portion is brought into the disable mode. Further, in order to prevent the clock signal from being delivered in the logic block 101 at the flip-flop circuit portion thereof when the flip-flop circuit portion is brought into the disable mode, the following two circuit arrangement strategies can be employed.
{circle around (1)} First strategy: the flip-flop circuit portion thereof is replaced with a flip-flop element having no enable terminal in the logic block 101 shown in FIG. 8. Further, the logic block 101 is provided with a gate so that a clock signal input to the flip-flop element can be controlled in accordance with an enable signal.
{circle around (2)} Second strategy: the function as the clock net 104 is assembled together with the lines 102 so that lines as the clock net can be changed in accordance with the desired type of the logic device. In this way, halting of clock signal supply can be controlled in a manner similar to that of the other logic device components. In more concretely, the clock signal supply itself through the lines 102 can be stopped by using the ordinary logic block 101.
However, if the logic device employs the above-introduced two strategies for preventing the clock signal from being supplied to the logic block 101 at the flip-flop circuit portion thereof upon the disable mode, the logic device will encounter the following difficulties.
Initially, in the first strategies identified by reference {circle around (1)}, although the electric power consumption brought about in the flip-flop circuit portion can be decreased, it will be difficult to arrange the wiring for supplying the clock signal to each of the logic blocks, which fact can lead to a clock skew. Thus, another buffer shall be inserted into the clock net for adjusting the clock skew. However, this buffer element will also consume electric power. To decrease the power consumption at the buffer element is additional task from the circuit design standpoint. Therefore, it is difficult to decrease the electric power consumption or heat generation of the entire device.
Further, in the first strategy identified by reference {circle around (2)}, it is true that electric power consumption at the flip-flop circuit portion can be decreased in the logic block. However, since the clock net is composed of a variable line, similarly to the above-case, it is necessary to insert a buffer element in the device for adjusting the clock skew. In this case, there is a fear that a considerable amount of the amount of logic circuit elements and lines tend to become idle, and hence utility of the components can be decreased. Thus, and it becomes difficult to keep the processing speed of the whole device at a high speed.
The present invention is made in view of the above aspect. Therefore, it is an object of the present invention to provide a programmable logic device which intends to reduce electric power consumption or heat generation sufficiently as a whole device while preventing a clock skew from being brought about and retaining a processing speed of the device. Further object of the present invention is to propose a method of controlling such a programmable logic device.
In order to attain the above object, according to the present invention, there is provided a programmable logic device including a plurality of logic blocks for carrying out logical operation, lines for connecting the logic blocks to one another, line-changing means for changing the state of lines connecting the logic blocks to one another by programming, a clock net for supplying a clock signal for controlling an operation timing to each of the logic blocks, the clock net being provided independently of the lines, and clock control means for dynamically controlling switching between a clock signal supply mode and a clock signal stop mode for each logic block so that at least one non-active logic block any of the logic blocks, which shifts from an active state to a non-active state, can be stopped from being supplied with the clock signal.
In more preferably, the clock control means is composed of a plurality of switching units, provided on the clock net, for switching between the clock signal supply mode and the clock signal stop mode.
Further, each of the switching units is provided on a clock supply line constituting the clock net at a point just behind a branch of the clock supply line as viewed from the upstream side of the clock supply stream. Also, when at least one of the plurality of switching units, which is stopped from being supplied with the clock signal, exists and at least one of the plurality of switching units exists on a downstream side of the switch unit in the clock signal stop mode, the switching unit on the downstream side is placed in the clock signal supply mode.
Further, the clock control means may be arranged to carry out switching between the clock signal supply mode and the clock signal stop mode in accordance with a control signal supplied from a predetermined one of the plurality of logic blocks. In this case, it is more preferable that the clock control means is arranged to receive the control signal through the lines and the line-changing means.
Further, the clock control means may be arranged to carry out switching between the clock signal supply mode and the clock signal stop mode in accordance with a control signal supplied from a predetermined one of the plurality of logic blocks. In this case, it is more preferable that the clock control means is arranged to receive the control signal through the lines and the line-changing means.
Each of the switching units may be arranged to have an AND gate which creates a logical product of the control signal and the clock signal and outputs the product to the side of the logic block. Each of the switching units may be arranged to have an OR gate which creates a logical add of the control signal and the clock signal and outputs the add to the side of the logic block. Alternatively, each of the switching units may be arranged to have a latch which effects a latching action in response to the control signal and the clock signal and an AND gate which creates a logical product of an output of the latch and the clock signal and outputs the product to the side of the logic block.
Further, each of the switching units may be arranged to have a latch which effects a latching action in response to the control signal and the clock signal and an OR gate which creates a logical add of an output of the latch and the clock signal and outputs the add to the side of the logic block.
Further, at least one of the plurality of switching units, which is disposed within an area of a downstream side of the clock net, may be arranged to have an AND gate or an OR gate which generates a logical product or a logical add of the control signal and the clock signal and outputs the product or the add to the side of the logic block, and at least one of the plurality of switching units, which is disposed within an area of an upstream side of the clock net, may be arranged to have a latch which effects a latching action in accordance with the control signal and the clock signal and an AND gate or an OR gate which generates a logical product or a logical add of an output of the latch and the clock signal and supplies the product or the add to the side of the logic block.
Further, each of the logic blocks may be arranged to include an element which operates in synchronism with the clock signal.
Further, according to the present invention, there is proposed a method of controlling a clock signal to be supplied to a programmable logic device comprising a plurality of logic blocks for carrying out logical operation, lines for connecting the logic blocks to one another, line-changing means for changing the state of wiring connecting the logic blocks to one another by programming, and a clock net for supplying a clock signal for controlling an operation timing to each of the logic blocks, the clock net being provided independently of the lines, the method including steps of outputting a control signal for halting a clock signal supply to at least one non-active logic block of the plurality of logic blocks which shifts from an active state to a non-active state, and halting the clock signal supply to the non-active logic block at a point just behind a branch of the clock supply line as viewed from the upstream side of the clock supply stream, in accordance with the control signal which is generated at the step of outputting the control signal.
When the above method is effected, an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device) is employed as the programmable logic device.
Therefore, according to the programmable logic device of the present invention, the clock control means dynamically control each of the logic blocks in the switching between the clock signal supply mode and the clock signal stop mode so that the clock signal is prohibited from being supplied to any logic block of the plurality of logic blocks placed in the non-active state. Accordingly, electric power consumption or heat generation as the whole circuit arrangement can be decreased.
Further, according to the arrangement of the present invention, the plurality of switching units are disposed just behind the corresponding branch point of the clock supply line forming the clocknet. Therefore, this arrangement of the clock supply line is free from a problem of clock signal skew, and components including an existing buffer disposed on the clock net can be properly controlled in switching between the clock signal supply mode and clock signal stop mode. Furthermore, according to the arrangement of the present invention, the control signal for each switching circuit is supplied from a corresponding logic block through the wiring. Therefore, each logic block can be controlled in switching between the clock supply mode and clock stop mode depending on the state of operation of the logic block. Thus, each logic block can be controlled with ease and large freedom will be brought into a situation of designing the property of control.
Moreover, according to the arrangement of the present invention, if there is any switching circuit on the downstream side with respect to a switching circuit which is set to the clock supply stop mode, the switching circuit disposed on the downstream side is inevitably set to the clock signal supply mode. Therefore, a control signal of an active state may be supplied to only the upstream side switching circuit which governs all of the logic blocks which are desired to be set to the clock signal stop mode. Accordingly, a plurality of logic blocks disposed on the downstream side can be collectively controlled in their clock control by providing a single supply of control signal, the switching circuits disposed on the downstream side need not be supplied with a control signal which brings the switching circuit into the active state, and hence the control becomes easy, and a number of circuit elements necessary for clock control can be decreased.